A conventional analog to digital converter (ADC) circuit generally includes two parts: one part is a sampling head, that is, a sample-and-hold circuit (namely, the so-called Switch-Cap circuit, also referred to as a sample-and-hold device). The hold circuit generally includes a metal-oxide semiconductor (MOS for short) switch and a capacitor, and is used to implement a sample-and-hold function. A reason for using the sample-and-hold circuit is that when analog to digital (A/D) conversion is performed on an analog signal, a particular conversion time is required from a conversion start to digital signal output upon a conversion end. In this conversion time, the analog signal needs to remain unchanged. If the analog signal changes, conversion precision cannot be ensured. Especially when the inputted analog signal has a high frequency, a large conversion error is caused. To resolve this problem, a level of the inputted signal needs to be held when the A/D conversion starts, and a change of the inputted signal needs to be tracked after the A/D conversion ends. The sample-and-hold circuit is equivalent to an “analog signal memory” in a hold phase. The inputted signal is sampled and held, and is compared with different thresholds in a comparator, and information about different bits may be obtained. This is a principle of a common ADC.
Specifically, after sampling and holding the inputted signal, the sampling head inputs the inputted signal to the comparator. The comparator needs to complete comparison of multiple bits in a single sampling clock. As shown in FIG. 1, FIG. 1 is an architecture of an existing high-speed ADC, including a voltage divider network, a comparator, and an encoder. Specifically, if the existing high-speed ADC is an N-bit precision ADC, the voltage divider network generally needs to include 2N resistors of an equal resistance, 2N−1 reference voltages are generated on the voltage divider network, and accordingly 2N−1 comparators (triangle symbols in the figure) are required. An inputted signal (sampled) on which A/D conversion needs to be performed gains access to an input end of each of the 2N−1 comparators, and the 2N−1 reference voltages generated on the voltage divider network separately gain access to the other input end of each of the 2N−1 comparators, so as to separately compare the inputted signal with the 2N−1 reference voltages. The two input ends of each comparator are respectively one positive and one negative. If positive input is greater than negative input, 1 is output. If positive input is not greater than negative input, 0 is output. A result obtained by the comparator is outputted to the encoder. The encoder obtains an N-bit binary number by calculation which indicates a value of the inputted signal. At this point, the analog to digital conversion is completed.
Though the architecture of the existing ADC shown in FIG. 1 is the fastest in current electrical ADC solutions, a rate of a sampling head is very limited because the sampling head in the prior aft is inherently limited by an electrical signal (for example, a capacitor), and a rate requirement in some scenarios cannot be met (for example, in a radio frequency signal processing scenario). Therefore, to improve a sampling rate, multiple sampling heads have to be used for parallel processing in some scenarios. For example, four sampling heads sometimes need to be set in front of a comparator circuit for parallel processing in an ADC circuit of a GHz magnitude. In addition, for some scenarios with a higher rate requirement, such as a 5 GHz scenario, a 10 GHz scenario, or a scenario with an even higher requirement, the foregoing conventional electrical ADC cannot meet a requirement. Therefore, how to further improve an ADC rate is a problem that urgently needs to be resolved, so as to meet a higher rate requirement in an application scenario.